AMS Verification Interview Questions : PLL

Wikipedia and famous book called B. Razavi, Design of Analog CMOS Integrated Circuits are my favorite references for PLL.


Q1. Can you draw Block level diagram of a PLL?


Q2. Why do we need a divider in a PLL feedback loop?


Q3. How does a feedback divider look like? How was the circuitry of the divider? What type of divider was it?


Q5. What was the frequency of the divider you worked on?


Q6. What is a VCO? What kind of VCO was used in the PLL and do you know the reason why?


Q7. While simulating PLL with a Fast SPICE simulator - Nanosim/Ultrasim/Finesim what challenges did you face and how did you deal with that?


[Hint] High Frequency of the system and the LPF. 


Q8. What settings in general you take care in the config file while simulating a PLL with Fast SPICE simulation tool?


[Hint] Accuracy of the VCO and the resolution of time.

Understanding Fast SPICE Simulators

SPICE (Simulation Program with Integrated Circuit Emphasis) is used today by IC designers and students for custom and analog IC designs who need the highest accuracy. Without SPICE we could never see the world that we see today!

Fast SPICE is like SPICE by reading a transistor-level netilst however it runs much faster by making assumptions about your circuit netlist and will partition the netlist automatically into smaller pieces which can then be solved more quickly. Fast SPICE simulators can be flat or hierarchical tools. Without the Fast SPICE Simulators Verification Engineer would have been launching one test case out of 100 and then would have gone for a month long vacation. After that also there is no surety that the simulation results are there or crashed!!


Other than partitioning a netlist for a faster simulation run with Fast SPICE simulation tools we can replace the modules in the design that a particular test case is not targeting to a model written in C, Verilog-AMS etc. This further increases the speed of the simulation and thus decreases the product's time to market.


Today, there are many tools in the market that help AMS Verification Engineers to do their job :


1. XA , latest tool from Synopsys
2. Nanosim, years old and still going strong tool from Synopsys
3. Ultrasim from Cadence
4. Finesim from Magma
5. HSIM from Synopsys


In SNUG 2009, a paper was presented (link given below) that shows that XA (which is acronym for Extreme Accuracy) is much faster and more accurate in co-simulations/ Mixed Signal Simulations than Nanosim. 


http://www.synopsys.com.cn/information/snug/2009/accelerated-mixed-signal-full-chip-verification-with-xa-vcs




But to understand how these Fast SPICE Simulators work there is an excellent paper from Springer - "A Perspective on Fast SPICE Simulation Technology".
To read the article Click here .


You can find here the answers for these questions - 


1. How SPICE is different from Fast SPICE?
2. How Fast SPICE simulators are able to make changes in the netlist so as to complete a simulation 100 to 1000 times faster than SPICE?
3. What algorithms or numerical analysis is used by Fast SPICE Technology?
4. How is partitioning done in the netlist by Fast SPICE Tools and how it is getting improved in the market?
5. How memories are run faster with the help of Fast SPICE Technology?

AMS Verification Interview Questions : ADC/DAC

One of my favorite references for ADC other than a quick look on wikipedia -
http://www.unirioja.es/cu/lzorzano/ABCs_of_ADCs.pdf

Q1. What do you mean by sampling?

Q2. What is quantization?

Q3. How does a ADC/ DAC works?

Q4. Name any one kind of ADC/ DAC that you worked on and explain the working in temrs of a block diagram.

Q5. What should be the relationship between the reference voltage and Input voltage of a SAR ADC?

Q6. Explain any one DAC.

Q7. What is the difference between INL and DNL?

Q8. Do you understand the data sheet of the ADC/DAC given in Design Spec?

Q9. What would be the points to observe on a Top Level Verification simulation output for an ADC or DAC?

AMS Verification Interview Questions : MOSFET

Q1. What is a MOSFET?
http://www.doe.carleton.ca/~tjs/21-mosfetop.pdf

Q2. What is the difference between MOSFET and BJT?
http://www.differencebetween.net/technology/difference-between-bjt-and-mosfet/

Q3. What are the different layers of a MOSFET?

Q4. What is the difference between a PMOS and NMOS?

Q5. What if I connect the Drain of PMOS with a higher voltage than its Source?

Q6. What is a Pinch-off Voltage?

Q7. What are the different modes of operation for an NMOS/PMOS?

Q8. What happens when a PMOS or NMOS is in saturation region and why do we call the MOS to be saturated in this region?

Q9. What is the region of a MOS or what is the voltage on the third terminal when :

a) NMOS ; Gate 0V ; Drain 1V ; Source = ?
b) NMOS ; Gate 2V ; Drain 0V ; Source = ?

Q10. What is a floating gate?

AMS Verification Aspirant ???

As I mentioned in my previous post that AMS Verification skill set has started acquiring some considerable amount of space, it would be one of the sought after jobs by experienced and freshers. 

So, to help those who aspire for this role, I am going to write my next few posts on the Interview Questions. 

Knowing "AMS Verification"

Fresh out of college and zeal to work is equal to a "dreamer". The first step into office and the official ID makes all of the first timers share a smile within themselves. I got the same tickling and I smiled within myself when I joined job for the first time. This is how I was told "Welcome to the AMS Team". That time anything that had "Analog" made me feel its surely design - "Analog Design". Verification was  not a good name in my world. But slowly and silently, I learned all the aspects of the Design process. Everyone must agree that Verification is the integral part of the Chip to Market. So, do I.

Around 5 to 6 years back all the job portals used to be filled with the RTL Verification requirements and No AMS requirement. Verification meant RTL Verification but there was no room for the AMS Verification. For quite some time, I have observed that emptiness is no more there and AMS Verification requirement is making its own space. Job portals are the best source to know what is going on in the industry and what is the next tool we need to get armed with.

Here, I see a plethora of RTL / Digital Verification or Analog Design but I did not see any Analog Mixed Signal Verification Blogs like that. So, here we are for the AMS Verification Engineers.

Hope the blog helps!

Why AMS Verification?

This questions is a very common one and often debated by the RTL Verification Engineers that I am verifying all the digital settings and controls and Analog Designer has already confirmed the working of the modules then why to waste time on Analog Mixed Signal Verification.

Imagine a scenario where an enable from digital powers up the power resource and the power resource output in-turn powers an amplifier and the amplifier works if it is enabled. Now, the power resource designer knows that it works and the amplifier module designer knows that the amplifier works. But imagine a scenario where there is a leakage inside the amplifier while it is not enabled then that can lead to the output of power provider block fall down. Here, AMS Verification comes into picture. RTL Verification although can verify the enables coming properly but the VHDL/Verilog Models of the analog blocks (power resource and amplifier) could never catch this issue.

Imagine another scenario where a PLL is enabled, once the PLL is enabled an OK signal is issued to the digital if the PLL is locked and desired frequency is at the output. This OK signal decides whether the clock divider module should be enabled by issuing an enable from digital. This loop can be verified with AMS Verification only.