Why AMS Verification?

This questions is a very common one and often debated by the RTL Verification Engineers that I am verifying all the digital settings and controls and Analog Designer has already confirmed the working of the modules then why to waste time on Analog Mixed Signal Verification.

Imagine a scenario where an enable from digital powers up the power resource and the power resource output in-turn powers an amplifier and the amplifier works if it is enabled. Now, the power resource designer knows that it works and the amplifier module designer knows that the amplifier works. But imagine a scenario where there is a leakage inside the amplifier while it is not enabled then that can lead to the output of power provider block fall down. Here, AMS Verification comes into picture. RTL Verification although can verify the enables coming properly but the VHDL/Verilog Models of the analog blocks (power resource and amplifier) could never catch this issue.

Imagine another scenario where a PLL is enabled, once the PLL is enabled an OK signal is issued to the digital if the PLL is locked and desired frequency is at the output. This OK signal decides whether the clock divider module should be enabled by issuing an enable from digital. This loop can be verified with AMS Verification only.